FPDP / FPDP II Digital Parallel I/O PMC Module

The FPDP II DPIO2 is the second generation high speed digital parallel input output PMC module from VMETRO. The new DPIO2 architecture handles the transfer speed requirements imposed by the 64-bit 66 MHz PCI interface and the FPDP II 400 MByte/s improved bandwidth. The advanced capabilities of the linked-list DMA controller combined with the I/O handling features of the front-end FPGA will handle most data frame formats used in the data acquisition and signal processing environments. The speed is achieved by using a clock rate of 50 MHz clocking data on both edges. The basic card comes with the standard FPDP TTL signaling. A mezzanine card can be added as a Personality Module for other signal standards such as LVDS, PECL and RS-422.

In large volume deliveries, the generous capabilities of the on-board FPGAs have potential for custom programming for special handling of data formats such as timestamp insertion and specific framing. The PCI Interface chip provides a 64-bit PCI bus master/slave interface with a linked list DMA engine. The parallel interface is available through the front panel connector. The logical interface is based on the FPDP protocol. The electrical interface can be TTL (FPDP compliant), RS-422/485, PECL or LVDS, depending on what version of the DPIO2 is used. The DPIO2 can be delivered with two FIFO sizes, either 32 or 128 Kwords. Different packing options are available: 1x32-bit, 2x16-bit or 3x10-bit can be selected, while 4x8-bit or 8x4-bit is available on request. That means that the front panel port can use less than 32-bits, but the data cycles on PCI will always will have the optimal width (32-bit or 64-bit). When using the DMA engine, both single and linked-list DMA is supported. For linked-list DMA, 64K of descriptors are set up in the onboard SSRAM (Synchronous Static RAM), eliminating PCI contention that would occur if the descriptors were stored in host memory.